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41509hkim vl-2643/n0508hkim vl-2625 no.a1056-1/64 LC89058W-E 1. overview the LC89058W-E is a digital audio interface receiver ic that demodulates signals according to a data transfer format between digital audio devices via the iec60958/61937 and jeita cpr-1205. it supports demodulation sampling frequencies of up to 192khz. the LC89058W-E can easily replace the existing lc 89057w-vf4 a-e. the LC89058W-E incorporates a number of features for its low cost and is opti mal for receiving digital data for av amplifiers and receivers. 2. features 2.1 clock ? built-in pll false lock prevention circuit to provide accurate lock. ? includes built-in oscillation amplifier and frequency divider for quartz resonator. ? output clock: 512fs, 256fs, 128fs, 64fs, 32fs, 16fs, 2fs, fs, 1/2fs, and 1/4fs. ? possible to set the oscillation amplifier (external input) clock output regardless of the pll status. ? generates transition period signal for switching between the pll clock and oscillation amplifier (external input) clock. ? allows the user to set the pll clock output frequency for each sampling frequency band of input data. 2.2 data ? can receive s/pdif and serial data at sampling frequencies of 32khz to 192khz. ? equipped with a total of 7 digital data input pins: 1 input pin with an amplifier and 6 input pins with 5v tolerable ttl level signal. ? can generate data to be demodulated and through output data separately from a maximum of 7 kinds of s/pdifs. ? equipped an s/pdif input data detection function. possible to monitor the data input status of 32khz to 192khz with microcontroller. continued on next page. ordering number : ena1056a cmos ic digital audio interface receiver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC89058W-E no.a1056-2/64 continued from preceding page. ? equipped with a serial data input pin. possible to switch with demodulation output automatically according to the state of the pll circuit. ? the fs reception range of s/pdif interface can be limited. LC89058W-E can be set to a no-signal input state if the reception range is exceeded. ? supports i 2 s data output that facilitates interfacing with dsp. 2.3 other ? supports multi-channel transfer and r eception, using master/slave function. ? equipped with a 4bits general-purpose i/o pins. th ey can be used for interface with peripheral ics. ? the general-purpose i/o pins can also serve as selector inputs. possible to switch with hdmi and xm-radio signals. ? generates a dts-cd/ld detection flag on detection of a dts synchronization signal. ? outputs interrupt signal for microcontro ller (interrupt source can be selected). ? calculates sampling frequen cy of input signal and ou tputs it from the terminal or microcontroller interface. ? outputs iec61937 burst preamble pc from microcontroller interface. ? outputs iec60958 bit 1 of channel status (non-pcm data delimiter bit). ? outputs emphasis information of channel status. ? can use up to four LC89058W-Es at the same time by setting the 2-bit chip address. ? runs on a single 3.3v power su pply (s/pdif input and microcontroller interface support 5v ttl interface.) ? sqfp48 package package dimensions unit : mm (typ) 3163b sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 11 2 13 24 25 36 37 48
LC89058W-E no.a1056-3/64 4. pin assignment 5. pin functions table 5.1 pin functions pin no. name i/o function 1 rxout1 o rx0-6 input s/pdif through output pin 1 2 rx0 i 5 (pd) 5v withstand voltage ttl input level compatible s/pdif input pin (connected to gnd when rx1 is set) 3 rx1 i(pd) co-axial compatible s/ pdif input pin (supported demodulation sampling frequency of up to 96khz) 4 rx2 i 5 (pd) 5v withstand voltage ttl input level compatible s/pdif input pin (connected to gnd when rx1 is set) 5 rx3 i 5 (pd) 5v withstand voltage ttl input level compatible s/pdif input pin 6 dgnd digital gnd 7 dv dd digital power supply (3.3v) 8 rx4 i 5 (pd) 5v tolerable ttl input leve l compatible s/pdif input pin 9 rx5 i 5 (pd) 5v tolerable ttl input leve l compatible s/pdif input pin 10 rx6 i 5 (pd) 5v tolerable ttl input leve l compatible s/pdif input pin 11 dv dd digital power supply (3.3v) 12 dgnd digital gnd 13 lpf o pll loop filter connection pin 14 av dd analog power supply (3.3v) 15 agnd analog gnd 16 rmck o r system clock ou tput pin (vco , 512fs, xin) 17 rbck o/i r system bit clock i/o pin (64fs) 18 dgnd digital gnd 19 dv dd digital power supply (3.3v) 20 rlrck o/i r system lr clock i/o pin (fs) 21 rdata o serial audio data output pin 22 sbck o s system bit clock output pin (16fs, 32fs, 64fs, 128fs) 23 slrck o s system lr clock output pin (fs/4, fs/2, fs, 2fs) 24 sdin i 5 external serial audio data input pin continued on next page. mout 39 38 37 di rerr slrck sdin do 36 42 41 40 45 44 43 48 47 46 cl ce dgnd xmode gpio0 dv dd gpio2 gpio1 rxout2 gpio3 int 35 ckst 34 a udio 33 32 31 LC89058W-E top view dv dd 30 xin 29 dgnd 28 27 dv dd 26 dv dd dgnd dgnd 25 xout xmck 23 24 2 1 rdata sbck dv dd rlrck rbck dgnd a gnd rmck lpf a v dd * rx5 * rx6 dv dd * rx4 * rx3 dgnd * rx1 * rx2 rxout1 * rx0 4 3 6 5 8 7 10 9 12 11 21 22 19 20 17 18 15 16 13 14 * : pull-down resistor internal at no selection
LC89058W-E no.a1056-4/64 continued from preceding page. pin no. name i/o function 25 dgnd digital gnd 26 dv dd digital power supply (3.3v) 27 xmck o oscillation amplifier clock output pin 28 xout o output pin connected to the resonator 29 xin i external clock input pin, connected to the resonator (12.288mhz/24.576mhz) 30 dv dd digital power supply 31 dgnd digital gnd 32 mout i/o emphasis information || input fs monitor output || chip address setting input pin 33 audio i/o channel status bit 1 output || chip address setting input pin 34 ckst i/o clock switching transition period signal out put || master/slave setting input pin 35 int i/o microcontroller interrupt signal output || pins44-48 i/o setting input pin 36 rerr o pll lock error, data error flag output pin 37 do o ccb microcontroller i/f, read data output pin (3-state) 38 di i 5 ccb microcontroller i/f, write data input pin 39 ce i 5 ccb microcontroller i/f, chip enable input pin 40 cl i 5 ccb microcontroller i/f, clock input pin 41 xmode i 5 system reset input pin 42 dgnd digital gnd 43 dv dd digital power supply (3.3v) 44 gpio0 o/i general-purpose i/o pin || selector input pin (output referred to rdata pin) 45 gpio1 o/i general-purpose i/o pin || selector input pin (output referred to rlrck pin) 46 gpio2 o/i general-purpose i/o pin || selector input pin (output referred to rbck pin) 47 gpio3 o/i general-purpose i/o pin || selector input pin (output referred to rmck pin) 48 rxout2 o rx0-6 input s/pdif through output pin 2 * input voltage: i= -0.3 to 3.6v, i 5 = -0.3 to 5.5v * output voltage: o= -0.3 to 3.6v * pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (pd). their level is fixed when they are unselected. * pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level. * pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level. * pin 35 serves as the input pin for configuring the i/o of pins 44 to 47 when pin 41 is held at the low level. * the dv dd and av dd pins must be held at the same level and turned on and off at the same timing to preclude latch-up conditions.
LC89058W-E no.a1056-5/64 6. block diagram figure 6.1 LC89058W-E block diagram microcontroller i/f 35 33 cbit, pc 41 int audio demodulation & lock detect data selector 24 36 xmode rerr sdin pll clock selector input selector 9 10 4 5 8 44 45 13 rx5 rx6 rx2 rx3 rx4 gpio0 gpio1 lpf 20 rlrck 16 rmck 22 sbck 23 slrck 1 rxout1 46 47 gpio2 gpio3 oscillation amplifier 29 xin 28 xout 27 xmck 34 ckst 39 ce 40 cl 38 di 37 do 2 3 rx0 rx1 48 rxout2 21 rdata 17 rbck 32 mout fs calculator clock divider
LC89058W-E no.a1056-6/64 7 common and different points betw een lc89057w-vf4a-e and LC89058W-E 7.1 common features table 7.1: common of lc89057w-vf4a-e and LC89058W-E functions (hardware/software compatibility) item lc89057w-vf4a-e LC89058W-E package sqfp48(9x9) supply voltage 3.3v single source dir reception range 32khz to 192khz oscillation amplifier input frequency 12.288mhz/24.576mhz 2-system-clock pin output rmck , rbck, rlrck, sbck, slrck sbck: 16fs, slrck: 1/4 output added s/pdif inputs 7 maximum (1 coaxial, 6 optical) serial data input sdin non-pcm flag output audio emphasis information output em pha (consumer and professional) mout (consumer only) dts-cd/ld detection function 14- bit format detection supported general-purpose i/o 4 bits chip address setting 4 addresses maximum (master/salve supported) mode setting external resistor 4 resistors used microcontroller interface ccb (sanyo-proprietary if) di input regulations has. register configuration 4 comm and address bits, 8 data bits 7.2 removed functions table 7.2: differences between lc89057w-vf4a-e and LC89058W-E (removed functions) item lc89057w-vf4a-e LC89058W-E function modulation and demodulation modulation removed (demodulation only) s/pdif unlock path switching yes removed external clock synchronization mode yes removed r and s system clock synchronization asynchronous syst em synchronization clock (selmtd, rcksel removed) data output format 16, 20, 24 bits/left-justified/right-justified msb, i 2 s right-justified removed (left-justified msb, i 2 s only) c, v, u pin output yes removed input fs computed output 16khz to 192khz 32khz to 192khz (fs < 32khz, removed) microcontroller interrupt signal yes (low pulse, low level output) pulse output mode removed (level output only) 7.3 added or modified functions table 7.3: differences between lc89057w-vf4a-e and LC89058W-E (added or modified functions) item lc89057w-vf4a-e LC89058W-E page oscillation amplifier initial setting suspend ed while pll is locked permanent operation 19 pll clock output 256fs or 512fs 512fs 20-26 master clock output multiple of input fs is outp ut multiple of input fs on each band is output 22 clock output when xin source no limitation rbck and sbck must 1/2 or less of rmck 23 clock switching clock count is preserved (to maintain continuity) sw itched during the ckst pulse output 25 rmck and ckst polarity polarity cannot be switched polarity can be switched 23, 25 s/pdif reception limitation reflected only to error flag. reflected to both error flag and clock output 26 s/pdif input detection range 32khz to 96khz (xin=24.57m/12.28mhz) 32khz to 192khz (xin=24.576mhz only) 27 input fs value monitor output microcontroller interface output only microcontroller interface and pin outputs 32 general-purpose i/o input pin no timing c ontrol polling supported (with interrupt) 36 general-purpose i/o input/output pin parallel i/o functi on only internal selector input also supported. 37
LC89058W-E no.a1056-7/64 7.4 differences in microcontroller registers 7.4.1 differences in write commands table 7.4: lc89057w-vf4a-e write register map addr setting item di15 di 14 di13 di12 di11 di10 di9 di8 0 all system testm 0 txopr rxopr intopf 0 doen sysrst 1 demodulator system pbsel1 pbsel0 fslim1 fslim0 rxmon aosel vosel uosel 2 master clock ampopr1 ampopr0 exsync pllopr xmsel1 xmsel0 xinsel pllsel 3 r system output clock xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 4 s system output clock xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 5 source switching 0 rdtmut rdt sta rdtsel 0 rcksel ocksel selmtd 6 data input/output rxoff rosel2 ro sel1 rosel0 ulsel risel2 risel1 risel0 7 output format slrckp sbckp rl rckp rbckp 0 ofsel2 ofsel1 ofsel0 8 int source selection empf slipo p crnw unpcm csrnw fs chg indet error 9 rerr conditions erwt1 erwt0 fserr resta xtwt1 xtwt0 reder resel 10 modulation system pi3 pi2 pi1 pi0 0 vmode visel uisel 11 modulation data tcksel 0 txmod1 txmod0 txmut tdtsel txlrp txdfs 12 test 0 0 0 0 0 0 0 0 13 test 0 0 0 0 0 0 0 0 14 test 0 0 0 0 0 0 0 0 15 test 0 0 0 0 0 0 0 0 table 7.5: LC89058W-E write register map addr setting item di15 di 14 di13 di12 di11 di10 di9 di8 0 system setting 1 testm 0 ?0? ?0? ?0? 0 doen sysrst 1 system setting 2 ?0? ?0? fslim1 fslim0 rxmon aosel ?0? mosel 2 master clock ampopr1 ampopr0 ?0? pllopr xmsel1 xmsel0 xinsel ?0? 3 r system output clock xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 4 s system output clock xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 5 source switching 0 rdtmut rdtsta rdtsel 0 0 ocksel 0 6 data input/output 1 ?0? rosel2 rosel1 rosel0 ?0? risel2 risel1 risel0 7 output format slrckp sbckp rl rckp rbckp 0 ?0? ?0? ofdsel 8 int source selection empf gpio p crnw unpcm csrnw fs chg indet error 9 rerr condition setting erwt1 erwt0 fserr resta ?0? ?0? reder resel 10 general-purpose i/o pi3 pi2 pi1 pi0 0 ?0? ?0? ?0? 11 test ?0? 0 ?0? ?0? ?0? ?0? ?0? ?0? 12 system setting 3 0 0 ckstp rmckp 0 plldv1 plldv0 pllacc 13 data input/output 2 0 rxsel2 rxsel1 rxsel0 edtmut emckp extsel gpios 14 other output settings fssel1 fssel0 0 0 ptoxw1 ptoxw0 0 0 15 test 0 0 0 0 0 0 0 0 ? except mosel, prsel [1:0], ofdsel, gpio, selmtd an d rcksel, the command address of any inadvertently specified commands that are rem oved from the lc89057w-vf4a-e is assumed to be ?0? and ignored. the new commands added to the LC89058W-E are allocated to command addresses 12, 13, and 14.
LC89058W-E no.a1056-8/64 7.4.2 differences in read commands table 7.6: changes in the register function between lc89057w-vf4a-e and LC89058W-E ccb address lc89057w-vf4a-e LC89058W-E 0xe9 dit channel status write register removed table 7.7: differences in read register s between the lc89057w-vf4a-e and LC89058W-E lc89057w-vf4a-e LC89058W-E register 0xea 0xeb 0xea 0xeb do0 rxdet0 po0 rxdet0 po0 do1 rxdet1 po1 rxdet1 po1 do2 rxdet2 po2 rxdet2 po2 do3 rxdet3 po3 rxdet3 po3 do4 rxdet4 fsc0 rxdet4 fsc0 do5 rxdet5 fsc1 rxdet5 fsc1 do6 rxdet6 fsc2 rxdet6 fsc2 do7 rxdet7 fsc3 0 fsc3 do8 oerror fsdat0 oerror - do9 oindet fsdat1 oindet - do10 ofschg fsdat2 ofschg - do11 ocsrnw fsdat3 ocsrnw - do12 ounpcm fsdat4 ounpcm - do13 opcrnw fsdat5 opcrnw - do14 oslipo fsdat6 ogpio - do15 oempf fsdat7 oempf - do16 csbit1 - csbit1 - do17 iec1937 - iec1937 - do18 dts51 - dts51 - do19 dtses - dtses - do20 f0512 - 0 - do21 f1024 - 0 - do22 f2048 - 0 - do23 f4096 - 0 - ? the ccb addresses 0xec and 0xed remain the same for both the lc89057w-vf4a-e and LC89058W-E.
LC89058W-E no.a1056-9/64 7.5 points to notice about replacing ? when replacing the lc89057w -vf4a-e with the lc 89058w-e, it may be necessary to review the circuit pattern design of the printed circuit board in advance depending how the device is used. particular attention should be directed to pins 44 to 48 whose i/o functionality can be set according to the int pin setting. this section contains the notes and cautions to be observed when replacing the lc89057w-vf4a-e with the LC89058W-E. for details of the int pin, see chapter 9, initial system settings and chapter 10, description of demodulation function. ? refer to the specifications of lc89057w-vf4a-e when replacing LC89058W-E with lc89057w-vf4a-e. table 7.8: differences between lc89057w-vf4a-e and LC89058W-E (pins 44 to 48) int pin lc89057w-vf4a-e LC89058W-E modulation function general- purpose i/o func tion s/pdif pin.44 pin.45 pin.46 pin.47 pin.48 pin.44 pin.45 pin.46 pin.47 pin.48 tmck tbck tlrck tdata txo gpio0 gpio1 gpio2 gpio3 rxout2 pull-down input input input input output input input input input output general-purpose i/o function gener al-purpose i/o f unction s/pdif pin.44 pin.45 pin.46 pin.47 pin.48 pin.44 pin.45 pin.46 pin.47 pin.48 pio0 pio1 pio2 pio3 pioen gpio0 gpio1 gpio2 gpio3 rxout2 pull-up in/output in/output in/output in/output inpu t output output output output output 7.5.1 change from lc89057w-vf4a-e to lc89058w 7.5.1 when the int pin is set to pull-down figure 7.1 change from lc89057w-vf4a-e to LC89058W-E (when the int pin is set to pull-down) ? in this case, the system that doesn't use a modulation function or a general-purpose i/o function can be replaced with LC89058W-E. ? after the replacement, LC89058W-E is used on condition that it pins 44 to 47 connect with gnd and pin 48 open. lc89057w-vf4a-e int tlrck tdata tbck txo tmck pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 LC89058W-E int gpio2 gpio3 gpio1 rxout2 gpio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 print board
LC89058W-E no.a1056-10/64 7.5.1.2 when the int pin is set to pull-up 7.5.1.2.1 in case of ?pin 48 = gnd? figure 7.2 change from lc89057w-vf4a-e to LC89058W-E (when the int pin is set to pull-up) 1 ? after the replacement, pins 44 to 47 can be used as general purpose i/o output function. (pin 48 open) ? it is necessary to review the circuit pattern of the printed circuit board because the i/o setting of pin 48 differs from each other. 7.5.1.2.2 in case of ?pin 48 = v dd ? figure 7.3 change from lc89057w-vf4a-e to LC89058W-E (when the int pin is set to pull-up) 2 ? it is necessary to review the circuit pattern of the printed circuit board to change the pull-up resistor of pin 35 to the pull-down resistor because pins 44 to 47 is used as general purpose i/o input function. ? it is necessary to review the circuit pattern of the printed circuit board because the i/o setting of pin 48 differs from each other. lc89057w-vf4a-e int pio2 pio3 pio1 pioen pio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 LC89058W-E int gpio2 gpio3 gpio1 rxout2 gpio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 print board jp open when LC89058W-E use lc89057w-vf4a-e int pio2 pio3 pio1 pio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 LC89058W-E int gpio2 gpio3 gpio1 rxout2 gpio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 print board pioen jp jp open when LC89058W-E use
LC89058W-E no.a1056-11/64 7.5.2 change from LC89058W-E to lc89057w-vf4a-e 7.5.2.1 when the int pin is set to pull-down figure 7.4 change from LC89058W-E to lc89057w-vf4a-e (when the int pin is set to pull-down) ? it is necessary to review the circuit pattern of the printed circuit board to change the pull-up resistor of pin 35 to the pull-down resistor because pins 44 to 47 is used as general purpose i/o input function. ? it is necessary to review the circuit pattern of the printed circuit board because the i/o setting of pin 48 differs from each other. ? after the replacement, the rxout2 output of lc89057w-vf4a-e cannot be used. 7.5.2.2 when the int pin is set to pull-up figure 7.5 change from LC89058W-E to lc89057w-vf4a-e (when the int pin is set to pull-up) ? after the replacement, pins 44 to 47 can be used as general purpose i/o output function. however, it is necessary to review the circuit pattern of printed circuit board because pin 48 has to gnd. ? after the replacement, the rxout2 output of lc89057w-vf4a-e cannot be used. LC89058W-E int gpio2 gpio3 gpio1 gpio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 print board rxout2 lc89057w-vf4a-e int pio2 pio3 pio1 pioen pio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 jp jp short when lc89057w-vf4a-e use LC89058W-E int gpio2 gpio3 gpio1 rxout2 gpio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 lc89057w-vf4a-e int pio2 pio3 pio1 pioen pio0 pin. 35 pin. 46 pin. 45 pin. 47 pin. 44 pin. 48 print board jp short when lc89057w-vf4a-e use
LC89058W-E no.a1056-12/64 8. electrical characteristics 8.1 absolute maximum ratings table 8.1: absolute maximum ratings at agnd = dgnd = 0v parameter symbol conditions ratings unit maximum supply voltage av dd max 8-1-1 -0.3 to +4.6 v maximum supply voltage dv dd max 8-1-2 -0.3 to +4.6 v input voltage 1 v in 1 8-1-3 -0.3 to v dd +0.3 (max.3.9v) v input voltage 2 v in 2 8-1-4 -0.3 to +5.8 v output voltage v out 8-1-5 -0.3 to v dd +0.3 (max.3.9v) v storage ambient temperature tstg -55 to +125 c operating ambient temperature topr -30 to +70 c maximum input/output current i in , i out 8-1-6 20 ma 8-1-1: av dd pin 8-1-2: dv dd pin 8-1-3: rx1, rbck, rlrck, xin, gpio0, gpio1, gpio2, gpio3 pins 8-1-4: rx0, rx2, rx3, rx4, rx5, rx6, sdin, di, ce, cl, xmode pins 8-1-5: rxout1, rmck, rbck, rlrck, r data, sbck, slrck, xmck, xout, mout, _________ audio pins, ckst, _____ int, rerr, do, gpio0, gpio1, gpio2, gpio3, rxout2 pins 8-1-6: per input/output pin 8.2 allowable operating ranges table 8.2: recommended operating conditions at agnd = dgnd = 0v ratings parameter symbol conditions min typ max unit supply voltage av dd , dv dd 3.0 3.3 3.6 v input voltage range 1 v in 1 8-2-1 0 3.3 av dd , dv dd v input voltage range 2 v in 2 8-2-2 0 3.3 5.5 v operating temperature topr -30 70 c 8-2-1: rx1, rbck, rlrck, xin, gpio0, gpio1, gpio2, gpio3 pins 8-2-2: rx0, rx2, rx3, rx4, rx5, rx6, sdin, di, ce, cl, xmode pins
LC89058W-E no.a1056-13/64 8.3 dc characteristics table 8.3: dc characteristic s at ta = -30 to 70c, av dd = dv dd = 3.0 to 3.6v, agnd = dgnd = 0v ratings parameter symbol conditions min typ max unit input, high v ih 0.7v dd v input, low v il 8-3-1 0.2v dd v input, high v ih 2.0 5.8 v input, low v il 8-3-2 -0.3 0.8 v output, high v oh v dd -0.8 v output, low v ol 8-3-3 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-4 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-5 0.4 v output, high v oh v dd -0.8 v output, low v ol 8-3-6 0.4 v input amplitude v pp 8-3-7 200 mv consumption current i dd 8-3-8 40 ma pull-down resistance r dn 8-3-9 25 50 100 k 8-3-1: cmos compatible: rbck, rlrck input pins during xin and slave settings 8-3-2: ttl compatible: input pins other than those listed above 8-3-3: i oh = ? 12ma, i ol = 8ma: rmck output pin 8-3-4: i oh = ? 8ma, i ol = 8ma: xout, xmck output pins 8-3-5: i oh = ? 4ma, i ol = 4ma: rxout1, rbck, rlrck, rdata, sbck, slrck, rerr, mout, gpio0, gpio1, gpio2, gpio3, rxout2 output pins 8-3-6: i oh = ? 2ma, i ol = 2ma: output pins other than those listed above 8-3-7: before capacitance of rx1 input pin, and reception freque ncy is possible up to 96khz. 8-3-8: ta=25 c, fs=96khz 8-3-9: rx0, rx2, rx3, rx4, rx5, rx6 input pins
LC89058W-E no.a1056-14/64 8.4 ac characteristics table 8.4: ac characteristic s at ta=-30 to 70c, av dd =dv dd =3.0 to 3.6v, agnd=dgnd=0v ratings parameter symbol conditions min typ max unit rx0, rx2 to rx6 fs frequency f rfs1 28 195 khz rx1 fs frequency f rfs2 28 108 khz rx0, rx2 to rx6 pulse width t wdi1 20 ns rx1 pulse width t wdi2 40 ns rx0 to rx6 duty factor t duy 40 60 % xin clock frequency f xf 8-4-1 12 25 mhz rmck clock frequency f mck 4 5 0m h z rmck clock jitter tj 200 ps rmck, rbck delay t mbo 10 ns rbck, rdata delay t bdo 10 ns rmck, sbck delay t mbo 8-4-2 10 ns sbck, rdata delay t bdo 8-4-3 10 ns 8-4-1 a frequency compatible with the xinsel setting must be applied to xin. 8-4-2: when rmck and sbck source clocks are identical 8-4-3: when sbck is the pll source clock figure 8.1 ac characteristics of demodulation function rmck (o) rbck (o) rdata (o) rlrck (o) rx0-6 (i) t duy t duy f mc k t wdi t wdi t bdo t mb o (rmckp=0)
LC89058W-E no.a1056-15/64 8.5 ccb microcontroller in terface ac characteristics table 8.5: ccb microcontroller interface ac characteristics at ta=-30 to 70c, av dd =dv dd =3.0 to 3.6v, agnd=dgnd=0v ratings parameter symbol conditions min typ max unit xmode pulse width, low t rst dw 200 s cl pulse width, low t cl dw 100 ns cl pulse width, high t cl uw 100 ns cl to ce setup time t ce setup 50 ns cl to ce hold time t ce hold 8-5-1 50 ns cl to ce hold time t ce hold 8-5-2 0 ns cl to di setup time t di setup 50 ns cl to di hold time t di hold 50 ns cl to ce hold time t cl hold 50 ns cl to do delay time t cl to do 20 ns ce to do delay time t ce to do 20 ns di pulse width t di dw 8-5-3 200 ns 8-5-1: cl has to lower before ce is h when cl is normal h clock. 8-5-2: only when data write with cl of normal h clock. 8-5-3: di has to l period for the reset period when di is normal h. figure 8.2 ccb microcontroller interface ac characteristics cl (i) ce (i) do (o) di (i) t cluw t cldw t cesetup t cehold t clhold t dihold t disetup t cetodo t cltodo hi-z t didw dv dd av dd xmode (i) t rstdw
LC89058W-E no.a1056-16/64 9. initial system settings 9.1 system reset (xmode) ? the system operates correctly when xmode is set to "h" after 3.0v or higher supply voltage is applied. when xmode is set to "l" after power is turned on, the system is reset. ? to set chip address, master/slave, or pins 44 to 47 i/o, 10k pull-down or pull-up resistors must be connected to mout, audio , ckst, and int . ? if none of mout, audio , ckst, and int are pulled down or pulled up, their pin state will get unstable when the settings are entered, resulting in wrong setting. pull-up or pull-down resistors must be connected to these pins without fail. table 9.1: pin names and settings setting pins mout chip address audio master/slave setting ckst pins 44 to 47 i/o setting int figure 9.1 setting timing chart of function setting input pins table 9.2: output pin state when xmode is reset (xmode=l) no. pin name pin state no. pin name pin state 1 rxout1 rxo output 32 mout input state 16 rmck xin output 33 audio input state 17 rbck low output 34 ckst input state 20 rlrck high output 35 int input state 21 rdata low output 36 rerr high output 22 sbck low output 37 do hi-z output 23 slrck high output 48 rxout2 low output 27 xmck xin output dv dd xmode 3.0v t t > 200 s normal system operation range setting completed set pin state setting input state output state undefined resetting setting completed setting input state output state
LC89058W-E no.a1056-17/64 9.2 chip address settings (mout, ___________ audio) ? the LC89058W-E comes with a function to set a unique chip address to allow the use of several LC89058W-E on the same microcontroller interface bus. ? in chip address setting, connect a 10k pull-down or pull-up resistor to mout and ____________ audio. by this setting, 4 kinds of chip addresses can be set at a maximum. ? chip addresses in the microcontroller interface are set with cal and cau provided as the first two bits on the lsb side. cal corresponds to the lower chip address and cau to the higher chip address. ? command writing is enabled by making the chip address settings with mout and ____________ audio identical to the chip addresses sent from the microcontroller. ? the chip address setting is required even when only one LC89058W-E is used in the system. if the chip address is not set, the chip address is undefined and the microcontroller cannot control the system. when the microcontroller is not used, a chip address-setting pin is input open while xmode is "l". be sure to connect either a pull-down resistor or a pull-up resistor to mout and ____________ audio. table 9.3: chip address settings (resistor connection) _____ audio mout cau cal pull-down pull-down 0 0 pull-down pull-up 0 1 pull-up pull-down 1 0 pull-up pull-up 1 1 figure 9.2 setting example of function setting input pin chip address setting master or slave setting pins 44 to 47 input or output setting cal=cau=0 master pins 44 to 47 output pins setting contents of above figure LC89058W-E mout audio ckst int connect to different circuits pull-down 10k pull-up 10k
LC89058W-E no.a1056-18/64 9.3 master/slave settings (ckst) ? a master/slave function that allows multi-channel sync hronized transfer using multiple LC89058W-Es is included. for this setting, connects either a 10k pull-down or a pull-up resistor to ckst. ? set to the master mode normally, when single lc89058 w-e ic is used. when multiple LC89058W-Es are used, set one of them to the master mode and the others to the slave mode. ? in the multi-channel synchronous transfer mode usin g multiple LC89058W-Es, connect rbck and rlrck (output) on the master side to rbck and rlrck (input) on the slav e side. also connect xmck on the master side to xin on the slave side. at this time, the polarity of rbck and rlrck, and the frequency of xin and xmck must be identical. ? the master/slave function runs correctly with the multiple LC89058W-Es connected. ? be sure to connect either a pull-down resistor or a pull-up resistor to ckst. ? always supply the clock to rbck and rlrck when the slave function is set. table 9.4: master/slave switching (register connection) ckst mode pull-down master pull-up slave table 9.5: clock pin state pin master mode slave mode rmck output output rbck output input rlrck output input 9.4 pins 44 to 47 i/o settings ( int ) ? pins 44 to 47 are provided with a bidirectional buffer. ? when setting i/o function of pins 44 to 47, connect a 10k pull-down or pull-up resistor to int . ? be sure to connect either a pull-down resistor or a pull-up resistor to int . table 9.6: pins 44 to 47 i/o settings (resistor connection) ___ int mode pull-down input. pull-up output.
LC89058W-E no.a1056-19/64 10 description of demodulation function 10.1 clocks 10.1.1 pll (lpf) ? the LC89058W-E incorporates a vco (voltage controlled oscillator) that can be stopped with pllopr and it synchronizes with sampling frequencies (fs) from 32khz to 192khz and with the data with transfer rate from 4mhz to 25mhz. pll is locked at 512fs. ? lpf is a pin for pll loop filter. connect the following resistance and capacitance shown in the figure. figure 10.1 loop filter configuration 10.1.2 oscillation amplifiers (xin, xout, xmck) ? the LC89058W-E features a built-in osc illation amplifier. connecting a quartz resonator, feedback resistor, and load capacitance to xin and xout can configure an oscillation circuit. when connecting a quartz resonator, use one with a fundamental wave. be aware that the load capacitance depends on the quartz resonator characteristics. ? if the built-in oscillation amplifier is not used and oscillation module is used as the clock source instead, connect the output of an external clock supply source to xin. at this time, it is not necessary to connect a feedback resistor between xin and xout. ? always supply xin with the 12.288mhz or 24.576mhz clock set with xinsel. if supplying other frequencies to xin, it is necessary to set that the result of change in samp ling frequency fs of input data with fserr is not reflected to an error flag. by this setting, th e operation functions properly. since it is not a recommended frequency, it cannot be used for input fs calculations. ? the setting of xinsel must be completed prior to s/pdif input. ? supply xin with clocks all the time to be used in the following applications. (1) detection of presence or absence of s/pdif input (2) clock source while pll is unlocked (3) calculation of input data sampling frequency (4) time definition when switching input data (5) external source of supply clock (clock fo r an ad converter, etc.) in xin source mode. (6) polling processing performed when setting the general-purpose i/o input function ? the oscillation amplifier runs even when the pll is locked. therefore, data detection and calculation of input sampling frequency become possible while the pll is locked. in that case, both the oscillation amplifier clock and the pll clock signals coexist, and then user must pay atten tion and make sure sound quality is not adversely affected. ? if adverse effects on the sound quality are recognized, it is possible to set with the ampopr [1:0] that the oscillation amplifier automatically stop operation while the pll is lo cked. therefore, setting of the ampopr [1:0] must be completed either prior to s/pdif input or while pll is unlocked. ? the oscillation amplifier can be stopped if it is unnecessa ry. however, when the normal operation is resumed, it must wait for 10ms or longer until the resonator oscillation gets stable. ? xmck outputs the xin clock. the xmck output is set with xmsel [1:0]. the xin clock can be set to 1/1, 1/2, 1/4, or muted output. ? if you use only the oscillation amplifier, input the quartz resonator to xin and xout or an external clock to xin, and fix the electric potential of digital data input pins of rx0 to rx6, or set with risel [2:0] that all the inputs are deselected. r0 : 220 c0 : 0.1 f c1 : 0.022 f lpf r0 c0 c1
LC89058W-E no.a1056-20/64 10.1.3 switching between master clock and clock source ? the rmck, rbck, and rlrck (hereunder, r system), and the sbck and slrck (hereunder, s system) clock sources can be selected between the following two master clocks. (1) pll source (512fs) (2) xin source (12.288mhz or 24.576mhz) ? clock source switching is to set with the r and s systems interlocked. this setting is carried out with ocksel. ? the clock source is automatically switched to the pll or xin clock by locking/unlocking the pll. the clock source can be switched to xin with ocksel, regardless of the pll status. table 10.1: relationship between clock source switch commands and clock sources when pll locked/unlocked r system clock source s system clock source ocksel locked unlocked locked unlocked 0 pll xin pll xin 1 xin xin xin xin ? the pll status can be always monitored with rerr even after switching to the xin source. moreover, the processed information can be read with the microcontro ller interface regardless of the pll status. 10.1.4 points to notice about switching clock source while pll is locked ? it is necessary to set the oscillation amplifier to the con tinuous operation mode at the same time with ampopr [1:0] to do the clock switch to the xin source with ocksel when the oscillation amplifier has stopped in the state where the pll is locked. the clock is not output when switching to the xin clock source without executing this setting. ? in the state where the pll is locked, if the clock is switched to xin source with ocksel while the oscillator amplifier is stopped, rerr is temporarily outputs an error (high level) indication. when switched to xin source, the oscillator amplifier is switched to the operating state at the same time. rerr is temporality outputs an error (h level) indicati on when the oscillation amplifier switches from the stop condition to the continuous mode. consequently the input fs calculation restarts. at this time, the previous fs calculation value is reset and compared with the newly calculated fs value. then those two values are found not identical, that?s why the error is temporarily issued.
LC89058W-E no.a1056-21/64 10.1.5 master clock block diagram (xin, xout, rmck, xmck) ? the relationships between the two types of pll and xin source master clocks, switching, and the frequency division function are described below. ? the contents in the quotation marks ?*** ? by the switch and function blocks correspond to the write command names. ? lock/unlock is automatically switched by pll locking/unlocking. figure 10.2 master clock block diagram pll 512fs 12.288m 24.567m 1/n (n=1,2,4) 1/n (n=1, 2) ?pllopr? s/pdif xin xout ?prsel[1:0]? ?ampopr[1:0]? rmck xmck ?xinsel? ?xrsel[1:0]? ?xmsel[1:0]? lock/unlock ?pllacc? auto 1/n (n=1,2,4) 1/n (n=1,2,4) ?plldv2? ?rmckp? gpio0 ?extsel? ?emckp? ?ocksel? ?plldv1?
LC89058W-E no.a1056-22/64 10.1.6 pll clock output ? the pll clock output is controlled by the pllacc, plldv1, plldv2, or prsel[1:0]. ? pllacc can be used to generate a pll lock frequency for each s/pdif input sampling frequency band. figure 10.3 pll clock output control table 10.2: pll clock output frequencies (bold settings are recommended values.) pll output pllacc=0 (fixed multiple outputs of input fs) pllacc= 1 (fixed multiple outputs for each input fs band) s/pdif fs prsel=00 (256fs) prsel=01 (512fs) prsel=10 (128fs) plldv0=0 plldv1=0 plldv0=1 plldv1=0 plldv0=0 plldv1=1 plldv0=1 plldv1=1 32khz 8.19mhz 16. 38mhz 4.09mhz 16.38mhz 8.19mhz 16.38m hz 8.19mhz 44.1khz 11.28mhz 22.57mhz 5.64mhz 22.57mhz 11.28mhz 22.57m hz 11.28mhz 48khz 12.28mhz 24. 57mhz 6.14mhz 24.57mhz 12.28mhz 24.57m hz 12.28mhz 64khz 16.38mhz 32. 76mhz 8.19mhz 16.38mhz 16.38mhz 32.76m hz 32.76mhz 88.2khz 22.57mhz 45.15mhz 11.28mhz 22.57mhz 22.57mhz 45.15m hz 45.15mhz 96khz 24.57mhz 49. 15mhz 12.28mhz 24.57mhz 24.57mhz 49.15m hz 49.15mhz 128khz 32.76mhz 65. 53mhz 16.38mhz 16.38mhz 16.38mhz 16.38m hz 16.38mhz 176.4khz 45.15mhz 90.31mhz 22.57mhz 22.57mhz 22.57mhz 22.57m hz 22.57mhz 192khz 49.15mhz 98. 30mhz 24.57mhz 24.57mhz 24.57mhz 24.57m hz 24.57mhz ? if 128khz, 176.4khz or 192khz input is received when the pllacc is set to 0 and the prsel [1:0] to 01, the dc characteristics of output directly sent to the rmck pin can not be guaranteed. in such a case, set the frequency to one half or quarter of the pll clock frequency (prsel [1:0]=00 or 10). s/pdif input 512fs lock detection fs calculation fs= 32k, 44.1k, 48k fs= 64k, 88.2k, 96k fs= 128k, 176.4k, 192k yes no yes no yes no ?pllacc? lock unlock pll output 256fs 1 0 pll fixation output ?prsel=00?: 256fs ?prsel=01?: 512fs ?prsel=10?: 128fs pll output free-run pll output 128fs pll output 512fs pll output 256fs * ?plldv0? pll output 512fs pll output 256fs ?plldv1? 1 0 1 0 *: when the data is judged to exceed the value of fslim [1:0] which limits the reception frequency of the input s/pdif, processing similar to pll unlocking is carried out and the processing does not proceed to the subsequent step. the clock source is automatically switched to the xin source.
LC89058W-E no.a1056-23/64 10.1.7 output clocks (rmck, rbck, rlrck, sbck, slrck) ? the LC89058W-E features two clock systems (r and s systems) in order to supply the various needed clocks to peripheral devices such as a/d converter and dsp. ? the clock output settings for the r and s systems ar e done with pllacc, plldv1, pllvd2, prsel[1:0], xrsel[1:0], xrbck[1:0], xrlrck[1:0], psbck[1:0 ], pslrck[1:0], xsbck[1:0], and xslrck[1:0]. ? setting range for each clock output pin when the pll is used as source (1) rmck: selection from 1/1, 1/2, and 1/4 of pllacc, plldv0, plldv1, or 512fs (2) rbck: 64fs output (3) rlrck: fs output (4) sbck: selection from 128fs, 64fs, 32fs, and 16fs (5)slrck: selection from 2fs, fs, 1/2fs, and 1/4fs ? setting range for each clock output pins when the xin is used as source (1) rmck: selection from 1/1, 1/2, and 1/4 of 12.288mhz or 24.576mhz (2) rbck: selection from 12.288mhz, 6.144mhz, and 3.072mhz (3) sbck: selection from 12.288mhz, 6.144mhz, and 3.072mhz (4) rlrck: selection from 192khz, 96khz, and 48khz (5) slrck: selection from 192khz, 96khz, and 48khz ? the polarity of rmck can be reversed with rmckp. ? the polarity of rbck, rlrck, sbck, and slrck can be reversed with rbckp, rlrckp, sbckp, and slrckp. table 10.3 list of output clock frequencies (bold items = initial settings) pll source (internal vco ck) xin source (xin input ck) output pin name 512fs 12.288mhz 24.576mhz rmck 512fs 256fs 128fs 12.288mhz 6.144mhz 24.576mhz 12.288mhz 6.144mhz rbck 64fs 12.288mhz 6.144mhz 3.072mhz (rmck=24.576mhz) (rmck 12.288mhz) (rmck 6.144mhz) rlrck fs 192khz 96khz 48khz sbck 128fs 64fs 32fs 16fs 12.288mhz 6.144mhz 3.072mhz (rmck=24.576mhz) (rmck 12.288mhz) (rmck 6.144mhz) slrck 2fs fs fs/2 fs/4 192khz 96khz 48khz notes: ? rbck and sbck output clock must not quicken more than rmck output clock frequency. also, rbck and sbck output clock are set to become 1/2 or less of rmck output clock at xin source. if it doesn?t follow these conditions, rbck and sbck clocks are not output.
LC89058W-E no.a1056-24/64 10.1.8 output clocks block diagram (rmck, rbck, rlrck, sbck, slrck, xmck) ? the relationships between the output clock and switch function are shown below. ? pll in the figure indicates the pll source and xin the xin source. ? the contents in the quotation marks ? ??? ? by the switch function blocks correspond to the write command names. ? the broken lines connecting the switches indicate coordinated switching. ? lock/unlock is switched automatically by pll locking/unlocking. figure 10.4 clock output block diagram 1/2 1/4 mute 1/1 ?pllacc? ?xrsel[1:0]? mute 12.288mh 6.144mhz 3.072mhz 64fs pll ?xrbck[1:0]? xin pll xin mute 192khz 96khz 48khz fs pll ?xrlrck[1:0]? xin 16fs mute 12.288mh 6.144mhz 3.072mhz pll ?xsbck[1:0]? ?psbck[1:0]? xin fs/4 mute 192khz 96khz 48khz pll ?xslrck[1:0]? ?pslrck[1:0]? xin 128fs 64fs 32fs 2fs fs fs/2 mute 1/1 1/2 ?xmsel[1:0]? ?ocksel? lock / unlock master clock generator pll source 512fs x?tal source 12.288mhz 24.576mhz slrck rbck rmck xmck sbck rlrck 512fs 1/2 1/4 512fs 256fs 128fs mute 1/1 12.288mhz 24.576mhz input fs ?prsel[1:0]? ?xinsel? auto ?plldv1? ?rmckp? ?sbckp? ?slrckp? ?extsel? gpio0 gpio1 gpio2 ?emckp? master / slave ?plldv0?
LC89058W-E no.a1056-25/64 10.1.9 output of clock switch transition signal (ckst) ? ckst outputs pulse when the output clock changes by pll lock/unlock. ? the polarity of the ckst pulse output can be reversed with ckstp. subsequently, ckstp is assumed to be 0. ? in the lock-in stage, the ckst falls at the word clock generated from the xin clock after pll is locked following detection of input data, and rises at the same timing as rerr after a designated period. ? in the unlock stage, the ckst falls at the same timing as rerr, pll lock detection signal, and rises after word clocks generated from the xin clock are counted for a designated period. ? change of the pll lock status and timing of the clock change can be seen by detecting the rising and falling edges and pulses of ckst. ? the clock is switched after the pll lock condition is test ed and identified. the timing of this clock switching is determined by setting the ptoxw [1:0]. the initial value is such that the clock is switched in 2.7ms after the falling edge of ckst. the value, however, assume s that the oscillation amplifier is set to permanent operation mode. if the oscillation amplifier is set to be stopped after pll locking, the startup time before the oscillation amplifier stabilizes after pll unlocking, is added. ? a free-running clock is output from the clock output pin immediately after pll unlocking. figure 10.5 clock switch timing digital data lock unlock 5.3ms same timing as rerr rx0 to rx6 pll status xin clock pll clock ckst rerr rmck (b): unlock stage (ckstp=0) rx0 to rx6 pll status xin clock pll clock ckst rerr rmck (a): lock-in stage digital data unlock lock after pll lock 3ms to 144ms (ckstp=0) xin clock pll clock pll clock xin clock 2.7ms 2.7ms** **: when set to ptoxw[1:0]=00 (max.)
LC89058W-E no.a1056-26/64 10.1.10 output clocks generated when input s/pdif reception is limited ? the same processing performed when the pll is unlocked is carried out if an s/pdif input exceeding the reception range limit (which can be defined by fslim[1:0]) is supplied. the clock source is then switched to the xin clock and clocks are output from respective clock pins. figure 10.6 output clocks generated when input data reception is limited din0-6 rmck rbck rlrck pll status fs=44.1khz fs=192khz lock pll clock rerr lock pll clock din0-6 pll status fs=44.1khz fs=192khz lock pll clock rerr lock xin clock fs=96khz lock pll clock fs=96khz lock pll clock din0-6 pll status fs=44.1khz fs=192khz lock pll clock rerr lock xin clock fs=96khz lock rmck rbck rlrck rmck rbck rlrck unlock xin clock (a) when set to fslim[1:0]=00 (no limit on inputs) (b) when set to fslim[1:0]=01 (receive frequency is limited to 96khz or lower) (c) when set to fslim[1:0]=10 (receive frequency is limited to 48khz or lower)
LC89058W-E no.a1056-27/64 10.2 s/pdif i/o 10.2.1 reception range of s/pdif input ? the guaranteed reception range of input data is shown below. table 10.4: s/pdif reception range (fslim [1:0]=00) pll output clock setting input data reception range 512fs 30khz to 192khz note: (1) reception range of rx1 is 32khz to 96khz. (2) pll output clock is frequency-divided with pllacc, plldiv and prsel [1:0] and is output from rmck. ? the fs reception range for input data can be limited within the set range of pll output clocks stated above. this setting is carried out with fslim [1:0]. when this func tion is adopted, input data exceeding the set range is considered as an error, the clock so urce is automatically switched to the xi n source, and rdata output data is subject to the rdtsel setting. 10.2.2 s/pdif i/o pins (rx0 to rx6, rxout1, rxout2) ? s/pdif input pins are 7 inputs at maximum. (1) rx1 is a coaxial-compatible input pin. when using rx1, connect rx0 and rx2 to gnd. (2) rx0, rx2, rx3, rx4, rx5, and rx6 are ttl input level pins with 5v-tolerance voltage. (3) make sure that the selected pins are not input-open. for points to notice on rx1, see the following subsection. (4) the unselected pins are pulled down with their internal resistors. ? the demodulation input and s/pdif through-output pins rxout1 and rxout2 data can be selected independently. (1) the demodulation data is selected with risel[2:0]. (2) the rxout1 output data is selected with rosel[2:0]. (3) the rxout2 output data is selected with rxsel[2:0]. ? it is possible to deselect all of rx0 to rx6 with risel[2:0] (risel[2:0]=111). ? rxout1 and rxout2 can be muted with rxosel[2:0] and rxsel[2:0], respectively. muting is recommended to reduce jitter when rxout1 and rxout2 are not used. ? the data input state can be monitored with the rxmon setting. the status of each data input pin is stored in ccb address 0xea and output registers do0 to do7. more over, the latest information can be read with the microcontroller by setting the interrupt processing comm and indet. for details, see chapter 12, microcontroller interface. ? the frequencies of input data that can be monitored with this setting is from 32khz to 192khz. the data detection function applies to iec60958 compatib le s/pdif data. the frequency of the clock supplied to xin when rxmon is set is limited to 24.576mhz. LC89058W-E does not run at any clock frequency other than 24.576mhz. moreover, since this function uses the xin clock, the oscillation amplifier must be set in the continuous operation mode when rxmon is set. ? when the data input monitoring is specified, the input pins, except rx1pin and those which are selected for demodulation, are pulled down. this is to preclude input-open when detecting no connection input pins. for the peripheral circuit of the rx1 pin, see the following page.
LC89058W-E no.a1056-28/64 10.2.3 s/pdif input circuits (rx0 to rx6) ? rx0, rx2, rx3, rx4, rx5, and rx6 can be received the data of 32khz to 192khz. ? rx1 can be received up to 96khz data. ? if rx1 with a built-in amplifier is us ed as a coaxial input pin, malfunction may occur due to the influence from the adjacent rx0 and rx2 input pins. to avoid the influences from those pins, fix rx0 and rx2 to "l". in addition, the pull-down resistor is inserted after the coupling capacitor for the noise measures, when the signal is not connected with rx1 is selected. ? when rx1 is selected and the input si gnal to rx1 is always fixed to either "h" or "l" (toslink etc), rx0 and rx2 processes are not required. ? rx0, rx2, rx3, rx4, rx5, and rx6 are ttl input level compatible s/pdif input pins with 5v-tolerance voltage. figure 10.7 s/pdif input circuits rx0 rx1 rx2 coaxial optical (a) coaxial input circuit (b) optical input circuit LC89058W-E rx0 rx1 rx2 LC89058W-E rx3 rx4 rx5 rx6 optical etc. rx3 rx4 rx5 rx6 optical etc. 470k
LC89058W-E no.a1056-29/64 10.3 serial audio data i/o 10.3.1 output data format (rdata) ? the output format is set with ofdsel. ? the initial value of output format is i 2 s. ? output data is output synchronized with the rlrck edge immediately after the rerr output becomes "l". figure 10.8 data output timing l-ch r-ch msb lsb msb lsb 24bit 24bit rlrck (o) rbck (o) rdata (o) l-ch r-ch msb lsb msb msb lsb 24bit 24bit rlrck (o) rbck (o) rdata (o) (0): i 2 s data output (1): msb-first front-loading data output
LC89058W-E no.a1056-30/64 10.3.2 serial audio data input format (sdin) ? LC89058W-E is provided with a serial data input pin of sdin. ? the format of the serial audio data input to sdin and the demodulation data output format must be identical. ? the initial value of modulation data output format is i 2 s. ? the sdin data to be input must be in synchronization with the rbck and rlrck clocks. ? the data input from the sdin pin is through-output to the rdata pin. ? the sdin pin must be connected to gnd when it is not used. figure 10.9 serial audio data input timing l-ch r-ch msb lsb msb lsb rlrck (o) rbck (o) rdata (o) l-ch r-ch msb lsb msb msb lsb 24bit 24bit rlrck (o) rbck (o) rdata (o) msb lsb msb lsb 24bit 24bit sdin (i) msb lsb msb msb lsb sdin (i) (0): i 2 s data output (1): msb-first front-loading data input
LC89058W-E no.a1056-31/64 10.3.3 output data switching (sdin, rdata) ? rdata outputs demodulation data when the pll is locked, and outputs sdin input data when the pll is unlocked. this output is automatically switched according to the pll locked/unlocked status. for details, see the timing charts below. ? when sdin input data is selected, switch to a clock source synchronized to the sdin data. ? with the rdtsta setting, the sdin input data is output to rdata regardless of the locked/unlocked status of the pll. ? with the rdtmut setting, the rdata output data can be also muted forcibly. ? even when the clock source is set to xin with ocksel and rcksel, the pll continues operating as long as the pll is not stopped with pllopr. at this time, the pll st atus is continuously output from rerr unless error output is forcibly set with resta. moreover, the processed in formation can be read with the microcontr oller interface regardless of the pll status. figure 10.10 timing chart of rdata output data switching pll status ckst rerr (a): lock-in stage unlock lock sdin data muted demodulation data rdata ckstp=0 (b): unlock stage pll status ckst rerr lock unlock sdin data muted demodulation data rdata ckstp=0
LC89058W-E no.a1056-32/64 10.3.4 data block diagram (rx0 to rx6, rxout1, rxout2, rdata, sdin) ? select the demodulated data and the sdin input data with rdtsel and rdtsta, and mute processing can be performed with rdtmut. ? moreover, gpio0 input data can be se lected with extsel. also, gpio0 can be subject to mute processing with edtmut. see chapter 11 for the selector function fo r the general-purpose i/o pins (gpio0 to gp1o3). figure 10.11 data system diagram 10.3.5 calculation of input data sampling frequency (mout) ? the input data sampling frequency is calculated using the xin clock. ? in the mode where the oscillation amplifier automatically stops according to the lock status of the pll, the input data sampling frequency is calculated during the rerr error peri od and completed when the oscillation amplifier stops with holding the value. therefore, the value remains unchanged until the pll becomes unlocked. ? if the oscillation amplifier is in a continuous operation mode, calculation is repeated constantly. even if sampling changes within the pll capture range for input data whose channel status sampling information does not change, the calculation results that follow the input data can be read. ? the calculation results can be readout via mout pin or with the microcontroller interface. since the mout pin is also used to generate the emphasis information, set the contents of the mout pin output by mosel. the fs calculation output to the mout pin is limited. the fssel[1:0] sets the contents of the mout pin output. table 10.5: mout pin output mode settings fssel1 fssel0 mout pin h output conditions 0 0 when calculating 32khz, 44.1khz or 48khz 0 1 when calculating 88.2khz or 96khz 1 0 when calculating 176.4khz or 192khz 1 1 when calculating 88.2khz, 96khz or higher rdata mux sdin rx0 rxout1 ?rdtsta? rx2 rx3 rx4 rx6 rx1 rx5 ?rdtsel? ?extsel? s/pdif ?risel[2:0]? ?rosel[2:0]=111? rxout2 s/pdif ?rxsel[2:0]=111? ?rdtmut? ?edtmut? gpio3 dir ?rosel[2:0]? ?rxsel[2:0]?
LC89058W-E no.a1056-33/64 10.4 error output processing 10.4.1 lock error and data error output (rerr) ? rerr outputs an error flag when a pl l lock error or a data error occurs. ? it is possible to treat non-pcm data reception as an error by the resel setting. ? the rerr output conditions are set with resta. since the pl l status can be output at all times, the pll status can be always monitored, even when the clock source is xin. 10.4.2 pll lock error ? the pll gets unlocked for input data that lost bi-phase mo dulation regularity, or input data for which preambles b, m, and w cannot be detected. however, even if preambles b, m, and w are detected if the timing does not conform to the iec60958, the pll get unlocked and processed. for example, period of preamble b is not every192 frames. ? rerr turns to ?h? when the pll lock error occurs and returns to ?l? when the data demodulation returns normal and ?h? is held for somewhere between 3ms to 144ms. this holding time is determined with the erwt[1:0] setting. ? the rising and falling edges of rerr are synchronized with rlrck. 10.4.3 input data parity error ? odd number of errors among parity bits in input data and input parity errors are detected. ? if an input parity error occurs 9 or more times in succe ssion, rerr turns to "h" indicating that the pll is locked, and after holding "h" for somewhere between 3ms and 144ms, it returns to "l". ? the error flag output format can be selected with reder, when an input parity error is output less than 8 times in succession. 10.4.4 other errors ? even if rerr turns to "l", the channel status bits of 24 to 27 (sampling frequency) are al ways fetched and the data of the previous block is compared with the current data. mo reover, the input data sampling frequency is calculated from the fs clock extracted from the input data, and the fs calcula ted value is compared in a same way as described above. if any difference is detected in these data, rerr is instantly made "h" and the same processing as for pll lock errors is carried out. ? the pll causes a lock error when the fs changes as desc ribed above. however, in order to support sources with a variable fs (for example a cd player with a variable pitc h function), it is possible to set with fserr not to output an error flag unless fs changes exceeding the pll capture range. in the fserr setting, when the pll is locked, rerr is turned to ?l? without reflecting the fs calculation result to the error flag concerning input data within reception range by fslim [1:0]. moreover, the data comparison at the channel status bits of 24 to 27 as described above is not performed. ? if a setting which regard non-pcm data input as an error is made with resel, rerr turns to ?h? when non-pcm data input is detected. at this time, the pll locked status and various output clocks are subject to the input data, but the output data is muted.
LC89058W-E no.a1056-34/64 10.4.5 data processing upon occurrence of errors (lock error, parity error) ? the data processing upon occurrence of an error is described below. if 8 or fewer input parity errors occur in succession and transfer data is pcm audio data, the data is replaced by the one saved each in l-ch and r-ch in the previous frame. however, if the transfer data is non-pcm data, the error data is output as it is. ? non-pcm data is the data of when bit 1 (audio sample word) of the channel status turns to "h" based on the data detected prior to the occurrence of the input parity error. ? output data is muted when a pll lock error occurs or a parity error occurs 9 or more times in succession. ? as for the channel status output, the data of the previous block is held in 1-bit units when a parity error occur 8 or fewer times in succession. table 10.6 data processi ng upon error occurrence data pll lock error input parity error (a) input parity error (b) input parity error (c) demodulation data ?l? ?l? previous value data output fs calculation result ?l? output output output channel status ?l? ?l? previous value data previous value data * input parity error (a): if occu rs 9 or more times in succession * input parity error (b): if occurs 8 or fe wer times in succession, in case of audio data * input parity error (c): if occurs 8 or fewer times in succession, in case of non-pcm burst data figure 10.12 example of data processing upon parity error occurrence l-1 r-1 l-2 r-2 l-3 r-3 l-4 r-4 l-5 r-5 l-6 r-6 l-7 r-7 l-8 r-8 input data 1occurrence rerr rlrck l-0 r-0 l-1 r - 0 l-2 r-2 l - 2 r - 2 l - 2 r - 2 l - 2 r - 2 l - 2 rdata r-ch l-ch r-ch 9 times or more: muting previous value data previous value data
LC89058W-E no.a1056-35/64 10.4.6 processing during error recovery ? when preambles b, m, and w are detected, pll becomes locked and data demodulation begins. ? demodulation data is output from the rlrck edge after rerr turns to "l". figure 10.13 data processing when data demodulation starts 10.5 data delimiter bit 1 output ( ________ audio ) ? ____________ audio outputs the channel status data delimiter bit 1 information. ? outputs bit 1 of the channel status that indicates whether the input bi-phase data is pcm audio data. ____________ audio is immediately output upon detection of rerr even during "h" output period. ? or-output with iec61937 or with the dts-cd/ld detection flag is also possible with aosel. table 10.7 ____________ audio output ______ audio output conditions l pcm audio data (cs bit 1 = "l") h non-audio data (cs bit 1 = "h") 10.6 emphasis information output (empha) ? mout can output whether there is 50/15 s emphasis parameter for consumer by switching the contents of mout output by mosel. ? mout is immediately output upon detection of rerr even during "h" output. table 10.8 mout output mout output conditions l no pre-emphasis h 50/15 s pre-emphasis 10.7 iec61937, dts-cd/ld detection flag output ? a function to output iec61937 and dts-cd/ld detection flag for non-pcm data is provided. ? dts-cd/ld is compatible with "14-bit format." ? when bit 1 of channel status is non-pcm data, the iec61937 sync signal is detected and detection flag is output. if bit 1 is pcm data, detection flag is not output. ? the dts-cd/ld sync signal detection is done based on the sync pattern and the base frequency. the sync pattern is checked every 4096th frame, and the detection status is held until the sync pattern is no longer verified. ? the iec61937 and dts-cd/ld detection flag s can be readout with th e microcontroller interface in addition to output to the ____________ audio pin by aosel. when the unpcm non-pcm signal output setting is selected through the int output contents setting, an interrupt signal is output from int detecting an iec61937 or dts-cd/ld sync signal. reading output register from this information can see details of n on-pcm signal. this informatio n is used to read out the output register and identify the details of the non-pcm signal ? the detection flags are cleared when fs is changed or when a pll lock error or data error occurs. rlrck lock signal rerr rdata ok 3ms to 144ms data output start from rwck edge immediately after rerr is lowered
LC89058W-E no.a1056-36/64 11 description of general-purpose i/o func tion (gpio0, gpio1, gpio2, gpio3) 11.1 initial settings ? when setting general-purpose i/os for input, pull down int with a 10k resistors. when settings general-purpose i/os for output, pull up int with a 10k resistor. see chapter 9 for int pin settings. ? if general-purpose i/os are set to the output pin, the serial data input from the microcontroller interface is converted to parallel data and output from of gpio0, gpio1, gpio2, and gpio3. ? if general-purpose i/os are set to the input pin, select one of the functions listed below with gpios. (1) store the parallel data input from the gpio0, gpio1, gp io2, and gpio3 in the intern al register and readout the contents of that register through th e microcontroller interface (gpios=0). (2) configure a 2-to-1 (4 bits wide) selector that selects e ither the audio format data and clock that are input to the gpio0, gpio1, gpio2, and gpio3 pins, or data and clock demodulated by the dir block. rmck, rbck, rlrck, and rdata are the ou tputs from the selector (gpios=1). 11.2 output function ? the data output directed to the gpio0, gpio1, gp io2, and gpio3 ar e stored at ccb address 0xe8, command address 10, input register bits di12 to di15, or register pi[3:0]. ? the data stored in pi[3:0] are transmitted out of the gpio0, gpio1, gpio2, and gpio3 pins. 11.3 input function 11.3.1 gpios=0 ? the data input to the gpio0, gpio1, gpio2, and gpio3 ar e taken into ccb address 0xeb, output register bits do0 to do3, or register po[3:0]. ? the data must be readout by setting the interrupt source gpio to int or at an arbitrary timing. the way in which the data is taken into the register depends on how it is readout. 11.3.1.1 gpio=1 (using int ) (1) xin must always be given the specified clock and set in continuous operating mode (default). (2) the data inputs to the gpio0, gpio1, gpio2, and gpio3 are taken into the register on a 24khz clock. (3) when the state of one of the data inputs changes, int turns to ?l? and suspends the da ta transfer to the register. (4) the interrupt sources for ccb address 0xea, output register do14, and register ogpio must be verified. (5) int turns ?h? and the data is held in the regist er immediately when address 0xea is readout. (6) the read data from the po[3:0] is tr ansferred to the microcontroller. at the same time, the data in the register is cleared. (7) the contents of the register are updated if int turns to ?l? before p0[3:0] is readout. 11.3.1.2 gpio=0 (not using int ) (1) the data inputs to the gpio0, gpio1, gpio2, and gpio 3 pins are taken in when the ccb address 0xeb is set. (2) the data read from the po[3:0] is tr ansferred to the microcontroller. at the same time, the data in the register is cleared.
LC89058W-E no.a1056-37/64 11.3.2 gpios=1 ? the figure below shows the relationship between gpio0, gpio1, gpio2, gpio3 which are input to the selector and the dir block signal, and rmck, rbck, rlrck, rdata which are output from the selector and the control signal. figure 11.1 selector configuration diagram table 11.1 selector i/o signals input pin or input signal extsel=0 extsel=1 pll lock state pll unlock state output pin gpio0 (pin 44) pll-mck xin-mck rmck (pin 16) gpio1 (pin 45) pll-bck xin-bck rbck (pin 17) gpio2 (pin 46) pll-lrck xin-lrck rlrck (pin 20) gpio3 (pin 47) pll-data sdin rdata (pin 21) note: the selector output generated when the pll is locked can be changed to the xin clock system by setting the ocksel and rcsel. ? extsel is enabled by setting gpios=1. when gpios=0 is set, the state of extsel=0 is output from each pin. ? the clock input to gpio0 can be inverted by emckp and sent to rmck. ? the data to be input to gpio3 must conf orm to the pll-data or sdin audio format. ? the data input to gpio3 can be muted by edtmut. ? emckp and edtmut are enabled when gpios=1 is set. ? the above settings are valid only when the master mode is set and must not be set when the slave mode is set. 4 gpio0 gpio3 gpio2 gpio1 44 45 46 47 4 sdin 24 dir pll-mck pll-data pll-lrck pll-bck xin-mck xin-lrck xin-bck 4 4 rmck rdata rlrck rbck 16 17 20 21 lock judgment 4 ?extsel? xm radio adc ?emckp? ?edtmut?
LC89058W-E no.a1056-38/64 12. microcontroller interface ( _____ int , cl, ce, di, do) 12.1 description of microcontroller interface 12.1.1 interrupt output ( ____ int) ? interrupts is output when a change has occurred in the pll lock status or output data information. ? interrupt output consists of the register for selecting the interrupt source, the ______ int pin that outputs that state transition, and the registers that store the interrupt source data. ? normally ______ int is held ?h? and output ?l? up on occurrence of an interrupt. follo wing ?l? output, it is cleared and returns to ?h? immediately when the interrupt source output register is readout. ? the interrupt sources can be selected among the following items. multiple sources can be selected at the same time with the contents of ccb address 0xe8 and command address 8. ______ int outputs or calculation result of the selected interrupt sources. ______ int output = (selected source 1) + (selected source 2) + ... + (selected source n) table 12.1 interrupt source setting contents no. command name description 1 error output when rerr pin status has changed 2 indet output when input data pin status has changed (subj ect to oscillation amplifier operation condition) 3 fschg output when input fs calculation result has changed. (subject to oscillation amplifier condition) 4 csrnw output when channel status data of first 48 bits have updated 5 unpcm output when ______ audio pin status has changed 6 pcrnw output when burst preamble pc has been updated 7 gpio output when the state of input data changes when the general-purpose i/o parallel input is set. 8 empf output when emphasis information has changed ? the contents of set interrupt source are saved in outp ut registers do8 to do15 of ccb address 0xea, when the source occurs. however, for the read registers for source items 1 and 5, the each status of the rerr and ____________ audio pins are output at the time of reading. other data except for so urce items 1 and 5 are saved in the registers upon occurrence of an interrupt source. ? concerning source items 2 and 3, the oscillation amplifier cl ock is used. therefore, if the status is monitored even while the pll is locked, the oscillation amplifier must be set to the continuous operation mode. ? clearing ______ int at the same time of readout of an output register is carried out immediately after the output register 0xea is set. however, ______ int is not cleared other than the 0xea setting.
LC89058W-E no.a1056-39/64 12.1.2 ccb interface ? the ccb interface is a sanyo?s original serial bus format based on lsb-fi rst communication, but three-state is employed instead of open-drain for the data output format of LC89058W-E. ? data input/output is performed following ccb address input. the same ccb address cannot be used for both read and write operation. table 12.2 relationship between regi ster i/o contents and ccb addresses register i/o contents r/w ccb address b0 b1 b2 b3 a0 a1 a2 a3 function setting data input write 0xe8 0 0 0 1 0 1 1 1 input detection, interrupt output read 0xea 0 1 0 1 0 1 1 1 fs data output read 0xeb 1 1 0 1 0 1 1 1 cs data output read 0xec 0 0 1 1 0 1 1 1 pc data output read 0xed 1 0 1 1 0 1 1 1 12.1.3 data write procedure ? input is performed in the following sequence: ccb addresses of a0 to a3 and b0 to b3, chip addresses of di0 and di1, command addresses of di4 to di7, and data of di8 to di15. di2 and di3 are reserved for the system. so, di2 and di3 input must be doing "0". ? for the chip addresses, di0 corresponds to cal (low-order), and di1 to cau (high-order). for details, see section 9.2. 12.1.4 data read procedure ? read data is output from do. do is in the high impedance state when ce is "l", and begins outputting from the rising edge of ce after output setting is established at the ccb address. do then returns to the high impedance state at the falling edge of ce. ? if do outputs are shared using multip le LC89058W-E units, it is possible to set the do outputs of the LC89058W-E units of which data is not to be read to be always in th e high impedance state with doen. with this setting, only the targeted outputs can be read. 12.1.5 points to notices when normal h clock is used ? the ccb interface uses cl of a normal l clock, and it is also possible to use cl of a normal h clock. however, input the clock based on ccb microcontroller interface ac characteristics. ? cl is lowered before ce is raised when data reads.
LC89058W-E no.a1056-40/64 12.1.6 i/o timing figure 12.1 input timing chart (normal l clock) figure 12.2 input timing chart (normal h clock) (cl need not be lowered before ce is raised.) figure 12.3 output timing chart (normal l clock) figure 12.4 output timing chart (normal h clock) (cl is lowered before ce is raised, and do0 need be read with port) b1 ce cl do cal di hi-z b0 b2 b3 a0 a1 a2 a3 cau di2 di3 di4 di5 di6 di7 di8 di9 di10 di1 di2 ??? ??? di15 b1 ce cl do di hi-z b0 b2 b3 a0 a1 a2 a3 cau di2 di3 di4 di5 di6 di7 di8 di9 di10 di11 di12 ??? ??? di15 cal b1 ce cl do di hi-z b0 b2 b3 a0 a1 a2 a3 do1 do0 do2 do3 do4 do5 do6 do7 do8 ??? ??? ??? ??? ??? ??? don b1 ce cl do di hi-z b0 b2 b3 a0 a1 a2 a3 do0 do1 do2 do3 do4 do5 do6 do7 ??? ??? ??? ??? ??? ??? don ???
LC89058W-E no.a1056-41/64 12.2 write data 12.2.1 list of write commands ? a list of the write commands is shown below. ? to write the commands shown in the following table, set the ccb address to 0xe8. table 12.3 write register map add. setting items di15 di 14 di13 di12 di11 di10 di9 di8 0 system setting 1 testm 0 0 0 0 0 doen sysrst 1 system setting 2 0 0 fslim1 fslim0 rxmon aosel 0 mosel 2 master clock ampopr1 ampopr0 0 pllopr xmsel1 xmsel0 xinsel 0 3 r system output clock xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 4 s system output clock xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 5 source switch 0 rdtmut rdtsta rdtsel 0 0 ocksel 0 6 data i/o 1 0 rosel2 rosel1 rosel0 0 risel2 risel1 risel0 7 output format slrckp sbckp rlrckp rbckp 0 0 0 ofdsel 8 ___ intsource selection empf gpio p crnw unpcm csrnw fs chg indet error 9 rerr condition setting erwt1 erwt0 fserr resta 0 0 reder resel 10 general-purpose i/o pi3 pi2 pi1 pi0 0 0 0 0 11 test 0 0 0 0 0 0 0 0 12 system setting 3 0 0 ckstp rmckp 0 plldv1 plldv0 pllacc 13 data i/o 2 0 rxsel2 rxsel1 rxsel0 edtmut emckp extsel gpios 14 pll clock fssel1 fssel0 0 0 ptoxw1 ptoxw0 0 0 15 test 0 0 0 0 0 0 0 0 addr: command address ? the shaded parts of di8 to di15 in the command area are reserved bits. input must be doing "0". ? command addresses 11 and 15 are reserved for testin g purposes. writing to these addresses is prohibited.
LC89058W-E no.a1056-42/64 12.2.2 details of write commands ccb address: 0xe8; command address: 0; system setting 1 di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 testm 0 0 0 0 0 doen sysrst sysrst system reset 0: don't reset (initial value) 1: reset circuits other than command registers doen do pin output setting 0: output (initial value) 1: always high impedance state (read disabled) testm test mode setting 0: normal operation (initial value) 1: enter test mode ? when reset by sysrst is performed, rbck outputs ?l? and blrck outputs ?h.? ccb address: 0xe8; command address: 1; system setting 2 di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 0 fslim1 fslim0 rxmon aosel 0 mosel mosel mout output contents setting 0: output channel status emphasis information (initial value) 1: output input data fs calculation resu lts (output conditions ar e given by fssel[1:0].) aosel audio output mode 0: only output channel status bit 1 (initial value) 1: output channel status bit 1, iec61937 or dts-cd/ld detection flag rxmon setting digital audio data (s/pdif) input status monitoring 0: don?t monitor s/pdif input status (initial value). 1: monitor s/pdif input status fslim[1:0] setting of sampling frequency reception range for input digital signal 00: no limit (initial value) 01: fs 96khz (when exceeded, data is muted and clock is set to xin system output) 10: fs 48khz (when exceeded, data is muted and clock is set to xin system output) 11: reserved
LC89058W-E no.a1056-43/64 ccb address: 0xe8; command address: 2; master clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 0 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 ampopr1 ampopr0 0 pllopr xmsel1 xmsel0 xinsel 0 xinsel xin input frequency setting 0: 12.288mhz (initial value) 1: 24.576mhz xmsel [1:0] xmck output frequency setting 00: 1/1 of xin input frequency (initial value) 01: 1/2 of xin input frequency 10: 1/4 of xin input frequency 11: muted pllopr pll (vco) operation setting 0: operate (initial value) 1: stop ampopr [1:0] oscillation amplifier operation setting 00: permanent continuous operation (initial value) 01: reserved 10: automatic stopping of oscillation amplifier while pll is locked 11: stop ? in order to replace lc8905 7w-vf4a-e, setting contents of the ampopr[1:0] are different from those of lc89057w-vf4a-e.
LC89058W-E no.a1056-44/64 ccb address: 0xe8; command address: 3; r system output clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 0 1 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 xrlrck1 xrlrck0 xrbck1 xrbck0 xrsel1 xrsel0 prsel1 prsel0 prsel [1:0] setting of rmck output frequency while pll is locked (enabled when pllacc is set to ?0?) 00: 512fs1/2 (256fs) (initial value) 01: 512fs1/1 (512fs) 10: 512fs1/4 (128fs) 11: muted xrsel [1:0] setting of rmck output frequency during xin source 00: 1/1 of xin input frequency (initial value) 01: 1/2 of xin input frequency 10: 1/4 of xin input frequency 11: muted xrbck [1:0] setting of rbck output frequency during xin source 00: 3.072mhz output (rmck 6.144mhz) (initial value) 01: 6.144mhz output (rmck 12.288mhz) 10: 12.288mhz output (rmck=24.576mhz) 11: muted xrlrck [1:0] setting of rlrck output frequency during xin source 00: 48khz output (initial value) 01: 96khz output 10: 192khz output 11: muted ? don?t do the setting to which rmck=3.072mhz is output by xrsel [1:0]=10(1/4 output) setting when xin=12.288mhz is input because it doesn't satisfy the output setting condition of rbck and sbck. ? setting of xrbck [1:0] relate to setting of rmck output cl ock. rbck output clock is set to become 1/2 or less of rmck output clock at xin source.
LC89058W-E no.a1056-45/64 ccb address: 0xe8; command address: 4; s system output clock setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 xslrck1 xslrck0 xsbck1 xsbck0 pslrck1 pslrck0 psbck1 psbck0 psbck [1:0] setting of sbck frequency while pll is locked 00: 64fs output (initial value) 01: 128fs output 10: 32fs output 11: 16fs output pslrck [1:0] setting of slrck frequency while pll is locked 00: fs output (initial value) 01: 2fs output 10: fs/2 output 11: fs/4 output xsbck [1:0] setting of sbck frequency during xin source 00: 3.072mhz output (rmck 6.144mhz) (initial value) 01: 6.144mhz output (rmck 12.288mhz) 10: 12.288mhz output (rmck=24.576mhz) 11: muted xslrck [1:0] slrck output frequency setting during xin source 00: 48khz output (initial value) 01: 96khz output 10: 192khz output 11: muted ? setting of xsbck [1:0] relate to setting of rmck output clock. sbck output clock is set to become 1/2 or less of rmck output clock at xin source.
LC89058W-E no.a1056-46/64 ccb address: 0xe8; command address: 5; clock source switching; rdata output setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 rdtmut rdtsta rdtsel 0 0 ocksel 0 ocksel clock source setting 0: use xin clock as source while pll is unlocked (initial value) 1: use xin clock as source regardless of pll status rdtsel rdata output setting while pll is unlocked 0: output sdin data while pll is unlocked (initial value) 1: mute while pll is unlocked rdtsta rdata output setting 0: according to rdtsel (initial value) 1: output sdin input data regardless of pll status rdtmut rdata mute setting 0: output data selected with rdtsel (initial value) 1: muted ? when the oscillation amplifier is set to the permanent continuous operation mode with ampopr [1:0] or fs changes are set not to be reflected to the error flag with fserr, ocksel can switch the clock source while maintaining the rerr status. ? the phase of r system clock and s system clock synchronize. ? to input data to sdin, select a clock synchronized with the sdin input data. ? the xin source can be switched while maintaining the pll locked status. however, since switching between clock and data output can be set independently; it is recommended to select mute or sdin data for the output data when xin source is switched. ? if the oscillation amplifier is set to stop automatically wh en the pll gets locked, xin source switching from the pll locked status disables the clock output. be sure to set the oscillation amplifier to the continuous operation mode when switching the clock source to the xin source.
LC89058W-E no.a1056-47/64 ccb address: 0xe8; command address: 6; data i/o setting 1 di7 di6 di5 di4 di3 di2 di1 di0 0 1 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 rosel2 rosel1 rosel0 0 risel2 risel1 risel0 risel [2:0] data demodulation input pin setting 000: rx0 selection (initial value) 001: rx1 selection 010: rx2 selection 011: rx3 selection 100: rx4 selection 101: rx5 selection 110: rx6 selection 111: none are selected (all inputs are connected to gnd through pull-down resistors.) rosel [2:0] rxout1 output data setting 000: rx0 input data (initial value) 001: rx1 input data 010: rx2 input data 011: rx3 input data 100: rx4 input data 101: rx5 input data 110: rx6 input data 111: ?l? fixed output
LC89058W-E no.a1056-48/64 ccb address; 0xe8; command address: 7; data output format setting di7 di6 di5 di4 di3 di2 di1 di0 0 1 1 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 slrckp sbckp rlrckp rbckp 0 0 0 ofdsel ofsel audio data output format setting 0: i 2 s data output (initial value) 1: 24 bits, msb first, left-justification output rbckp rbck output polarity setting 0: falling rdata data change (initial value) 1: rising rdata data change rlrckp rlrck output polarity setting 0: "l" period: l-channel data; "h" period: r-channel data (initial value) 1: "l" period: r-channel data; "h" period: l-channel data sbckp sbck output polarity setting 0: falling rdata data change (initial value) 1: rising rdata data change slrckp slrck output polarity setting 0: "l" period: l-channel data; "h" period: r-channel data (initial value) 1: "l" period: r-channel data; "h" period: l-channel data
LC89058W-E no.a1056-49/64 ccb address: 0xe8; command address: 8; ______ int output contents setting di7 di6 di5 di4 di3 di2 di1 di0 1 0 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 empf gpio pcrnw unpcm csrnw fschg indet error error rerr signal output setting 0: don't output (initial value) 1: output rerr pin status change indet input data detection output setting 0: don't output (initial value) 1: output input data pin status change fschg setting of updated flag output of pll lock frequency calculation result 0: don't output (initial value) 1: output updated flag of pll lock frequency calculation result csrnw output setting for updated flag of first 48-bit channel status data 0: don't output (initial value) 1: output update flag of first 48-bit channel status data unpcm output setting for change flag of non-pcm data detection 0: don't output (initial value) 1: output ____________ audio pin status change pcrnw output setting for updated flag of burst preamble pc 0: don't output (initial value) 1: output updated flag of burst preamble pc gpio input data updated flag output setting when ge neral-purpose i/o parallel input is set (gpios=0) 0: don't output (initial value) 1: output input data updated flag empf output setting of emphasis detection flag 0: don't output (initial value) 1: output emphasis detection flag ? the input data detection output setting functions when indet=1 is set with the clock of 24.576mhz is supplied to the terminal xin (xinsel=1) and digital data input state monitoring function (rxmon=1) made effective. ? the channel status update flag compares th e first 48 bits of data of the previous block with those of the current block. if these data are identical, it outputs a flag , considering the data has been updated. ? the burst preamble pc update flag also compares the 16 bits of data of the pr evious block with those of the current data. if they are identical, an update flag is output. ? the 4-bit input data updated flag when the general-purpose i/o parallel input is set, is output only when a change has occurred in the sampling data with a clock of 24khz.
LC89058W-E no.a1056-50/64 ccb address: 0xe8, command address: 9; rerr output setting di7 di6 di5 di4 di3 di2 di1 di0 1 0 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 erwt1 erwt0 fserr resta 0 0 reder resel resel rerr output contents setting 0: pll lock error or data error (initial value) 1: pll lock error or data error or non-pcm data reder setting of parity error flag output within 8 times in a row 0: output only when non-pcm data is recognized (initial value) 1: output only during sub-frame for which error was generated resta rerr output condition setting 0: output pll status all the time (output pll status even during xin source) (initial status) 1: forcibly output error (set "h" to rerr forcibly) fserr setting of error flag output condition according to fs change 0: reflect fs changes to error flag (initial value) 1: don't reflect fs changes to error flag erwt [1:0] setting of rerr wait time after pll is locked 00: cancel error after preamble b is counted 3 (initial value) 01: cancel error after preamble b is counted 24 10: cancel error after preamble b is counted 12 11: cancel error after preamble b is counted 6 ? non-pcm data is identical to the detection data output to _________ audio. ? output data is muted if an error oc curs due to non-pcm data with resel. ? the resta setting is not reflected to the output pins of data and clock. ? for fserr, the fs calculation result obtained while the oscillati on amplifier is stopped is not reflected. in this case, fs changes consist of only cha nnel status fs information. ? erwt[1:0] defines the interval of time for rerr to out put error cancellation ("l") after pll is locked. since demodulated audio data is output after re rr cancels an error, you need to change this setting if the situation that the head of data is missing is a problem.
LC89058W-E no.a1056-51/64 ccb address: 0xe8; command address: 10; general-purpose i/o function di7 di6 di5 di4 di3 di2 di1 di0 1 0 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 pi3 pi2 pi1 pi0 0 0 0 0 pi0 contents of data output to the gpio0 pin when the general-purpose i/o parallel output is set 0: l (initial value) 1: h pi1 contents of data output to the gpio1 pin when the general-purpose i/o parallel output is set 0: l (initial value) 1: h pi2 contents of data output to the gpio2 pin when the general-purpose i/o parallel output is set 0: l (initial value) 1: h pi3 contents of data output to the gpio3 pin when the general-purpose i/o parallel output is set 0: l (initial value) 1: h
LC89058W-E no.a1056-52/64 ccb address: 0xe8; command address: 11; system settings 3 di7 di6 di5 di4 di3 di2 di1 di0 1 1 0 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 0 ckstp rmckp 0 plldv1 plldv0 pllacc pllacc pll clock lock frequency setting 0: manual setting (initial value) 1: automatic control (see 10.1.6.) plldv0 set the pll clock generated when 32khz, 44.1khz or 4 8khz is received with pllacc=1 0: 512fs output (initial value) 1: 256fs output plldv1 set the pll clock generated when 88 .2khz or 96khz is received with pllac=1 0: 256fs output (initial value) 1: 512fs output rmckp dir block rmck output setting 0: normal output (initial value) 1: inverted output ckstp ckst output polarity setting 0: normal high output (initial value) 1: normal low output
LC89058W-E no.a1056-53/64 ccb address: 0xe8; command address: 12; data i/o setting 2 di7 di6 di5 di4 di3 di2 di1 di0 1 1 0 1 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 0 rxsel2 rxsel1 rxsel0 edtmut emckp extsel gpios gpios setting of pins 44 to 47 input function (when int pull-down is set) 0: general-purpose i/o parallel input (initial value) i: selector input extsel rmck, rbck, rlrck, and rdata output setting 0: output data and clock of dir function (initial value). 1: output input signals to gpio0, gpio1, gpio2, gpio3 (gpios=1) emckp gpio0 output polarity setting (gpios=1) 0: normal output (initial value) 1: inverted output edtmut gpio3 mute setting (gpios=1) 0: normal output (initial value) 1: muted rxsel[2:0] rxout2 output data setting 000: ?l? fixed output (initial value) 001: rx0 input data 010: rx1 input data 011: rx2 input data 100: rx3 input data 101: rx4 input data 110: rx5 input data 111: rx6 input data ? gpios setting is needed when rmck, rbck, rlrc k, and rdata output are changed with extsel. ? rmck, rbck, rlrck, and rdata output don?t change ev en if it sets to extsel=1 in the state of gpios=0.
LC89058W-E no.a1056-54/64 ccb address: 0xe8; command address: 13; pll clock di7 di6 di5 di4 di3 di2 di1 di0 1 1 1 0 0 0 cau cal di15 di14 di13 di12 di11 di10 di9 di8 fssel1 fssel0 0 0 ptoxw1 ptoxw0 0 0 ptoxw[1:0] setting of clock switch wait time 00: clock switching after 2.67ms from when the pll lock status is identified (initial value) 01: clock switching after 1.33ms from when the pll lock status is identified 10: clock switching after 0.67ms from when the pll lock status is identified 11: clock switching after when the pll lock status is identified fssel[1:0] mout output contents se tting (output ?l? when pll unlock st atus or when a value other than those listed below is calculated) 00: output ?h? when 32khz/44.1khz/48khz is calculated (initial value) 01: output ?h? when 64khz/88.2khz/96khz is calculated 10: output ?h? when 128khz/176.4khz/192khz is calculated 11: output ?h?when 64khz/88.2khz/96khz or higher is calculated
LC89058W-E no.a1056-55/64 12.3 read data 12.3.1 list of read commands ? it is possible to read the following items. ? interrupt data output ? monitor output of digital data input status ? input data output when general-purpose i/o parallel input mode is set ? output of fs calculation result ? output of first 48 bits of channel status ? output of burst preamble pc data table 12.4 read register map 0xea 0xeb 0xec 0xed do0 rxdet0 po0 cs bit0 pc bit0 do1 rxdet1 po1 cs bit1 pc bit1 do2 rxdet2 po2 cs bit2 pc bit2 do3 rxdet3 po3 cs bit3 pc bit3 do4 rxdet4 fsc0 cs bit4 pc bit4 do5 rxdet5 fsc1 cs bit5 pc bit5 do6 rxdet6 fsc2 cs bit6 pc bit6 do7 0 fsc3 cs bit7 pc bit7 do8 oerror - cs bit8 pc bit8 do9 oindet - cs bit9 pc bit9 do10 ofschg - cs bit10 pc bit10 do11 ocsrnw - cs bit11 pc bit11 do12 ounpcm - cs bit12 pc bit12 do13 opcrnw - cs bit13 pc bit13 do14 ogpio - cs bit14 pc bit14 do15 oempf - cs bit15 pc bit15 do16 csbit1 - cs bit16 - do17 iec1937 - cs bit17 - do18 dts51 - cs bit18 - do19 dtses - cs bit19 - do20 0 - cs bit20 - do21 0 - cs bit21 - do22 0 - cs bit22 - do23 0 - cs bit23 - do24 - - cs bit24 - do25 - - cs bit25 - do26 - - cs bit26 - do45 - - cs bit45 - do46 - - cs bit46 - do47 - - cs bit47 -
LC89058W-E no.a1056-56/64 12.3.2 read register 0xea (s/pdif input detection, interrupt flag) output ccb address: 0xea, contents of read register output 1 do7 do6 do5 do4 do3 do2 do1 do0 0 rxdet6 rxdet5 rxdet4 rxdet3 rxdet2 rxdet1 rxdet0 rxdet0 rx0 input detection 0: no input data in rx0 1: input data exist in rx0 rxdet1 rx1 input detection 0: no input data in rx1 1: input data exist in rx1 rxdet2 rx2 input detection 0: no input data in rx2 1: input data exist in rx2 rxdet3 rx3 input detection 0: no input data in rx3 1: input data exist in rx3 rxdet4 rx4 input detection 0: no input data in rx4 1: input data exist in rx4 rxdet5 rx5 input detection 0: no input data in rx5 1: input data exist in rx5 rxdet6 rx6 input detection 0: no input data in rx6 1: input data exist in rx6 ? for readout of rxdet[10:0], rxmon must be set to "1" beforehand.
LC89058W-E no.a1056-57/64 ccb address; 0xea; contents of read register output 2 do15 do14 do13 do12 do11 do10 do9 do8 oempf ogpio opcrnw ounpcm oc srnw ofschg oindet oerror oerror rerr output (output status during readout) 0: no transfer error while pll is locked 1: transfer error exists or pll is unlocked oindet status change of data input pin (clear after readout) 0: no change in status of data input pin 1: change exists in status of data input pin ofschg result of updating input fs calculation (clear after readout) 0: no update of input fs calculation 1: input fs calculation is updated ocsrnw update result of first 48 bits channel status (clear after readout) 0: not updated 1: updated ounpcm ____________ audio output (output of status during readout) 0: non-pcm signal not detected 1: non-pcm signal detected opcrnw update result of burst preamble pc (clear after readout) 0: not updated 1: updated ogpio update result of input date when the general-purpose i/o parallel input mode is set (gpios=0) (clear after readout) 0: not updated 1: updated oempf channel status emphasis detection (output of status during readout) 0: no pre-emphasis 1: 50/15 s pre-emphasis exists ? concerning oerror and ounpcm, the status of rerr and ____________ audio that are subject to resel setting are read regardless of the _______ intoutput setting.
LC89058W-E no.a1056-58/64 ccb address: 0xea; contents of read register output 3 do23 do22 do21 do20 do19 do18 do17 do16 0 0 0 0 dtses dts51 iec1937 csbit1 csbit1 channel status bit 1 detection 0: pcm 1: non-pcm iec1937 iec61937 burst preamble detection 0: pa, pb not detected 1: pa, pb detected dts51 dts-cd/ld 5.1 channel sync signal detection 0: dts-cd/ld sync signal not detected 1: dts-cd/ld sync signal detected dtses dts es-cd/ld 6.1 channel sync signal detection 0: dts es-cd/ld sy nc signal not detected 1: dts es-cd/ld sync signal detected
LC89058W-E no.a1056-59/64 12.3.3 read register 0xeb (general-purpose i/o para llel input contents, fs calculation results) output ccb address: 0xeb, contents of read register output do7 do6 do5 do4 do3 do2 do1 do0 fsc3 fsc2 fsc1 fsc0 po3 po2 po1 po0 po0 contents input to the gpio0 pin when the general-purpose i/o parallel input mode is set (gpios=0). 0: l 1: h po1 contents input to the gpio1 pin when the general-purpose i/o parallel input mode is set (gpios=0). 0: l 1: h po2 contents input to the gpio2 pin when the general-purpose i/o parallel input mode is set (gpios=0). 0: l 1: h po3 contents input to the gpio3 pin when the general-purpose i/o parallel input mode is set (gpios=0). 0: l 1: h fsc [3:0] input data fs calculation result "xxxx": see code table. table 12.5 code table of input fs calculation result (ta = 25c, av dd = dv dd = 3.3 v) fsc3 fsc2 fsc1 fsc0 target frequency 0 0 0 0 out of range 0 0 0 1 - 0 0 1 0 - 0 0 1 1 - 0 1 0 0 - 0 1 0 1 - 0 1 1 0 - 0 1 1 1 32khz 1 0 0 0 44.1khz 1 0 0 1 48khz 1 0 1 0 64khz 1 0 1 1 88.2khz 1 1 0 0 96khz 1 1 0 1 128khz 1 1 1 0 176.4khz 1 1 1 1 192khz
LC89058W-E no.a1056-60/64 12.3.4 read register 0xec (readout of first 48 bits of channel status) output ? the first 48bits of channel status can be read. ? the readout channel status data is output with lsb first. ? for readout, set the ccb address to 0xec. ? the channel status data cannot be updated after the ccb address is set. ? the relation between the read registers and the channel status data is shown below. table 12.6 read registers of first 48 bits of channel status register bit no. contents register bit no. contents do0 bit 0 application do24 bit 24 sampling frequency do1 bit 1 control do25 bit 25 do2 bit 2 do26 bit 26 do3 bit 3 do27 bit 27 do4 bit 4 do28 bit 28 clock accuracy do5 bit 5 do29 bit 29 do6 bit 6 not defined do30 bit 30 not defined do7 bit 7 do31 bit 31 do8 bit 8 category code do32 bit 32 word length do9 bit 9 do33 bit 33 do10 bit 10 do34 bit 34 do11 bit 11 do35 bit 35 do12 bit 12 do36 bit 36 not defined do13 bit 13 do37 bit 37 do14 bit 14 do38 bit 38 do15 bit 15 do39 bit 39 do16 bit 16 source number do40 bit 40 do17 bit 17 do41 bit 41 do18 bit 18 do42 bit 42 do19 bit 19 do43 bit 43 do20 bit 20 channel number do44 bit 44 do21 bit 21 do45 bit 45 do22 bit 22 do46 bit 46 do23 bit 23 do47 bit 47
LC89058W-E no.a1056-61/64 12.3.5 read register 0xed (burst preamble pc data) output ? the burst preamble pc data can be read with the demodulation function. ? the 16 bit-data of burst preamb le pc are output with lsb first. ? for readout, set the ccb address to oxed. ? the relation between the read register and burst preamble pc data is shown below. table 12.7 burst preambl e pc read registers register bit no. contents do0 bit 0 data type do1 bit 1 do2 bit 2 do3 bit 3 do4 bit 4 do5 bit 5 reserved do6 bit 6 do7 bit 7 error do8 bit 8 data type dependent do9 bit 9 information do10 bit 10 do11 bit 11 do12 bit 12 do13 bit 13 bit stream number do14 bit 14 do15 bit 15
LC89058W-E no.a1056-62/64 12.3.6 burst preamble pc field ? the burst preamble pc field is shown below. ? for the latest information, re fer to official specifications. table 12.8 burst preamble pc field register value contents do4 to 0 0 null data 1 dolby ac-3 data 2 reserved 3 pause 4 mpeg-1, layer 1 data 5 mpeg-1, layer 2, 3 data, or non-extended mpeg-2 6 extended mpeg-2 data 7 reserved 8 mpeg-2, layer 1, low sampling rate 9 mpeg-2, layer 2, 3, low sampling rate 10 reserved 11 dts type1 12 dts type2 13 dts type3 14 atrac 15 atrack2/3 16 to 26 reserved 27 reserved (mpeg-4, aac data) 28 mpeg-2, aac data 29 to 31 reserved do6, 5 0 reserved (set to "0") do7 0 error flag indicating effective burst payload 1 error flag indicating burst payload error do12 to 8 data type dependent information do15 to 13 0 bit stream number. (set to "0")
LC89058W-E no.a1056-63/64 13 application example table 13.1 application example element symbol recommended parameter application remarks cc 0.1 f power supply de-coupling ceramic capacitor rp 10k function setting pull-down/pull-up resistor cx 1pf to 33pf quarts resonator load cera mic capacitor with np0 characteristics rf 1m oscillation amplifier feedback rd 150 to 330 oscillation amplifier current limit ci 0.1 f to 0.01 f coaxial input dc cut ceramic capacitor ri 75 coaxial input termination c0 ?? pll loop filter ( ?? : see section 10.1.1) c1 ?? pll loop filter ( ?? : see section 10.1.1) r0 ?? pll loop filter ( ?? : see section 10.1.1) o p tical in p ut cc cc rf rd cx cx 12.288mhz 24.576mhz m-computer cc cc c1 c0 r0 adc dac dsp rxout1 rx0 rx2 rx3 dgnd rx4 rx5 rx6 dv dd dgnd int ckst av dd lpf agnd rmck rbck dgnd dv dd rlrck rdata sbck slrck sdin gpio3 rxout2 gpio2 gpio1 gpio0 dv dd dgnd xmode cl ce di do LC89058W-E sqfp48 (9x9) 37 38 39 40 41 42 43 44 45 46 47 48 34 33 32 31 30 29 28 27 26 25 36 35 24 23 22 21 20 19 18 17 16 15 14 13 3 7 8 9 10 11 12 4 5 6 1 2 dv dd rx1 audio dgnd dv dd xmck xout xin dv dd dgnd mout rerr cc cc cc hdmi r p r p r p r p chip address chip address master/slave expand/selecto r coaxial input ci ri
LC89058W-E no.a1056-64/64 ps this catalog provides information as of april, 2009. specifications and info rmation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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